1. Field
Example embodiments may relate to apparatuses and/or methods that may program data in memory devices. Additionally, example embodiments may relate to multi-bit (multi-level) programming apparatuses and/or methods that may program data in multi-level memory devices.
2. Description of Related Art
A single-level cell (SLC) memory device may store one bit of data in a single memory cell. The SLC memory may be referred to as a single-bit cell (SBC) memory. The SLC memory may store and read data of one bit at a voltage level which may be included in two distributions that may be divided by a threshold voltage level programmed in a memory cell.
For example, when a voltage level read from the memory cell is greater than 0.5V and less than 1.5V, it may be determined that the data stored in the memory cell has a logic value of “1”. When the voltage level read from the memory cell is greater than 2.5V and less than 3.5V, it may be determined that the data stored in the memory cell has a logic value of “0”. The data stored in the memory cell may be classified depending on the difference between cell currents and/or cell voltages during the reading operations.
A multi-level cell (MLC) memory device that may store data of two or more bits in a single memory cell may provide higher integration of memory. The MLC memory device may also be referred to as a multi-bit cell (MBC) memory. However, as the number of bits stored in the single memory cell increases, reliability may deteriorate and read-failure rate may increase. To store ‘m’ bits in a single memory cell, 2m voltage level distributions may be required. But, since the voltage window for a memory cell may be limited, the difference in threshold voltage between adjacent bits may decrease as ‘m’ increases, which may cause the read-failure rate to increase. For this reason, it may be difficult to improve storage density using a MLC memory device.
Accordingly, MLC memory devices may be widely used and thus error correction codes (ECC) or error control codes, which may detect an error occurring during data storing and reading operations and may correct the detected error, may be actively used.
Example embodiments may provide new multi-level (multi-bit) programming apparatuses and methods which may reduce the complexity ECC implemented in hardware.